WAT/CP Test Data Analysis: Unlocking the Yield Code from Massive Datasets

Author: MST Semiconductor | Category: Semiconductor Process Optimization | Keywords: WAT, CP Test, Yield Analysis, Semiconductor Data Analytics

First, Let Us Clarify: What Do WAT and CP Actually Measure?

People frequently confuse WAT and CP, thinking both are just “testing wafers.” In fact, what they measure, when they measure it, and the questions they answer are completely different.

WAT (Wafer Acceptance Test), also called PCM (Process Control Monitor), does not measure your product die. Instead, it measures dedicated test structures — TEGs (Test Element Groups) located in the scribe lines of the wafer. The timing is after all front-end processes are complete, before dicing. In essence, WAT answers the question: “How well were the processes executed on this batch of wafers?”

CP (Circuit Probe), also known as wafer sort or EWS (Electrical Wafer Sort), comes after WAT and uses probe cards to test each individual die directly. It answers the question: “Is this die functional?” After testing, each die is assigned to a bin — Bin 1 is good, while other bins correspond to different failure modes.

To use a rough analogy: WAT is like a physical health checkup, evaluating whether your metrics are normal. CP is like a job qualification exam, directly determining whether you can work. Passing the checkup does not guarantee passing the exam, but if your checkup metrics are drifting, the exam is very likely to show problems too.

What WAT Actually Measures

WAT measures device-level electrical parameters; the specifics depend on your process platform. For a typical BCD process that I worked on, there were 87 WAT parameters — and that was not even considered many. The main categories include:

MOSFET parameters: Threshold voltage Vth (measured for both NMOS and PMOS, at multiple channel lengths), saturation drain current Idsat, subthreshold swing SS, and drain-induced barrier lowering DIBL. These directly reflect gate oxide quality and channel doping levels. I once saw a 30mV Vth shift that was ultimately traced back to a 2% dose drift in ion implantation.

Resistance parameters: Polysilicon sheet resistance Rsp, metal layer sheet resistance Rs, contact resistance Rc, and via resistance Rvia. These parameters significantly impact digital circuit timing and are even more critical for analog circuits. Elevated Rc typically points to incomplete contact etch or barrier layer deposition issues.

Junction characteristics: PN junction breakdown voltage BV and leakage current. Power devices place particular emphasis on BV, as it directly determines whether the rated voltage specification is met. We once had a 40V LDMOS where BV dropped from 42V to 38V, scrapping the entire lot. The root cause was traced to a void in the STI fill.

Capacitance and reliability structures: Gate oxide capacitance Cox, TDDB test structures, and electromigration test lines. These are directly tied to long-term reliability.

Each wafer typically has 9 to 17 test sites, distributed across the center, edge, and intermediate regions. A standard 25-wafer lot yields 225 to 425 sets of WAT data. With 87 parameters per set, a single lot produces nearly 20,000 data points.

What CP Measures

CP is the test that directly confronts every single die. On a 300mm wafer, depending on die size, there may be anywhere from a few hundred to over ten thousand die. The number of test items per die can range from dozens to thousands, depending on product complexity.

CP testing falls broadly into two categories:

Parametric testing: Physically measuring each pin’s static current IDD, output drive capability, reference voltage accuracy, ADC INL/DNL, and similar parameters. These results are continuous values suitable for distribution analysis.

Functional testing: Applying test patterns to the die and checking whether the outputs are correct. Digital logic is primarily verified this way, with binary pass/fail results.

After testing, each die receives a bin code. Typically Bin 1 is fully passing good die, Bin 2 might be downgraded parts (e.g., not meeting the highest speed grade but still usable), and Bin 3 onward corresponds to various failure causes. A mature product’s CP yield can exceed 95%, but for new products in initial production, 60%-70% is common — yield ramp-up starts from this stage.

Just How Much Data Are We Talking About?

I have run the numbers. Assume a 300mm wafer with 600 die, 200 CP test items, and a 25-wafer lot. CP data alone amounts to 600 x 200 x 25 = 3 million data points. A production line running 10 lots per day produces 900 million CP data points per month. Add WAT data, test timestamps, bin codes, and wafer map coordinates, and the raw data volume easily reaches tens of gigabytes per month.

And that is just one product on one line. A fab running a dozen products simultaneously multiplies the data volume by another order of magnitude.

Traditional Analysis Methods: Useful, but Increasingly Insufficient

The traditional methods for WAT/CP analysis are actually quite mature:

Calculate mean and standard deviation, compute Cpk, and assess whether process capability is adequate. A Cpk above 1.33 is the minimum; above 1.67 is comfortable. Plot trend charts to check for parameter drift over time. Draw wafer maps to examine the spatial distribution of failed die — is it an edge effect, a localized cluster, or random?

I still use these methods today; the fundamentals cannot be abandoned. But where do the problems lie?

First, too many dimensions. Reviewing trend charts one by one for 87 WAT parameters takes half a day per lot. For 200 CP parameters, it is out of the question. Human bandwidth is limited, so in practice engineers typically monitor only a few “key parameters,” checking others only when problems arise. But sometimes the issue is precisely in the parameter you were not watching.

Second, inter-parameter correlations are invisible. For example, if Vth shifts by a modest 15mV with Cpk still passing, no single-parameter alarm would be triggered. But if Idsat simultaneously shifts 3% and Ron shifts 5%, three parameters moving together strongly suggest that some process window is at its edge. The human brain struggles to process this kind of multi-parameter joint signal.

Third, bridging analysis between WAT and CP is impractical manually. WAT parameters are at test-site resolution while CP data is at die-level resolution; the spatial resolutions differ, and correlation analysis requires spatial interpolation and alignment — a massive manual effort.

AI Methods: Not Replacing Engineers, but Helping Them See What They Cannot

In several actual projects, we have progressively introduced data-driven analysis methods. We stepped on plenty of pitfalls, but we also saw real results. Here are a few directions we are actively pursuing:

Multi-Parameter Correlation Analysis and Anomaly Detection

Apply PCA (Principal Component Analysis) to all WAT parameters simultaneously, projecting the 87-dimensional data onto a few principal components. Under normal conditions, data points cluster in a fairly compact region. When a lot’s data point falls outside this region, the anomaly is immediately visible — even if every individual parameter is still “within spec.”

We once caught a hidden issue exactly this way: a lot’s WAT data showed all parameters within spec and acceptable Cpk values, but the PCA score clearly deviated from the historical distribution. The root cause turned out to be a 0.02um lithography alignment offset. The impact on any single parameter was small, but the cumulative effect caused CP yield to drop by 3 percentage points. With traditional SPC charts alone, this signal would have been easily missed.

Tracing WAT Drift Back to Upstream Processes

WAT parameters are the “fingerprint” of upstream process results. When WAT parameters exhibit systematic drift, the issue necessarily lies in one or more preceding process steps. The traditional approach relies on engineering experience — Vth drift probably means implant issues, high Rc probably means contact etch issues. But this experience does not always apply to new processes or products.

Our current approach is to build correlation models between WAT data and upstream equipment data (e.g., power settings for each etch step, temperature and rate for each deposition, beam current and dose for implantation). Using Random Forest or gradient boosting trees, we identify which upstream process parameters have the greatest impact on WAT outcomes. Once trained, when WAT drift occurs, we feed in recent equipment data and the model identifies the top 3 suspect process steps and chambers.

In practice, accuracy is not 100%, but it consistently narrows the investigation scope from “the entire line’s dozens of process steps” to “3-5 steps,” significantly improving engineering troubleshooting efficiency. In one instance, the model pointed to a PVD target’s remaining lifetime — something we had not considered at all. After 3,500 wafers, film thickness uniformity had begun to degrade, but the thickness monitor had not yet alarmed. The WAT Rs parameter detected it first.

CP Spatial Pattern Recognition

The distribution pattern of failed die on a CP wafer map is extremely valuable for root cause identification. An edge ring pattern typically points to coating or etch edge effects; a fan-shaped pattern may relate to ion implantation angle; a repeatedly failing fixed position may indicate a probe card problem rather than a wafer problem.

Using CNNs (Convolutional Neural Networks) to classify wafer maps into common spatial patterns, then matching against a known root cause database, is especially useful in volume production. Many problems are recurring — the first occurrence might take two weeks to diagnose, but the second time the model identifies it in seconds and immediately tells you what the previous root cause was.

Closing the Loop with Virtual Metrology (VM)

Finally, let me discuss the relationship between WAT/CP data and Virtual Metrology, because these are fundamentally parts of one closed loop.

Virtual metrology uses real-time sensor data from equipment (FDC data) to predict wafer metrology outcomes. The advantage is that you do not have to wait for actual measurement — every wafer gets a “predicted value.” But VM model accuracy requires continuous calibration, and the calibration benchmark is WAT measured data.

Our current approach is: the VM model first produces WAT predictions for each wafer. When actual WAT data becomes available, it is compared against the predictions. If the deviation is within acceptable bounds, the model remains valid. If the deviation suddenly increases, either the process has shifted (requiring model retraining) or the metrology itself has an issue. This feedback loop enables the VM model to adaptively track process drift, rather than being trained once and left unattended.

Extending downstream, CP yield can also be estimated from WAT data. If WAT parameters show a trending deviation, a prediction can be made before CP testing, allowing engineering resources to be allocated proactively rather than scrambling after CP results reveal a yield drop. This lead time is extremely valuable in production, as several days may elapse between front-end process completion and CP testing — detecting the issue one day earlier means one fewer day of lost production capacity.